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integrated circuit systems, inc. ICS93716 0420h?09/10/08 block diagram low cost ddr phase lock loop clock driver pin configuration 28-pin ssop and tssop recommended application: ddr clock driver product description/features: low skew, low jitter pll clock driver i 2 c for functional and output control feedback pins for input to output synchronization spread spectrum tolerant inputs bypass mode on b revision only switching characteristics: peak - peak jitter (66mhz): <75ps cycle - cycle jitter (>100mhz):<65ps output - output skew: <100ps output rise and fall time: 550ps - 950ps functionality s t u p n is t u p t u o e t a t s l l p d d v at n i _ k l cc n i _ k l ct k l cc k l ct t u o _ b fc t u o _ b f v 5 . 2 ) m o n ( lhlhlh n o v 5 . 2 ) m o n ( hlhlhl n o v 5 . 2 ) m o n ( z h m 0 2 ICS93716 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
2 ICS93716 0420h?09/10/08 pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 8 2 , 5 1 , 1 1 , 6d n gr w pd n u o r g 1 , 5 , 4 1 , 6 1 , 5 2 , 7 2) 0 : 5 ( c k l ct u o. s t u p t u o r i a p l a i t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o c " 2 , 4 , 3 1 , 7 1 , 4 2 , 6 2) 0 : 5 ( t k l ct u o. s t u p t u o r i a p l a i t n e r e f f i d f o k c o l c " e u r t " 3 2 , 2 1 , 3d d vr w pv 5 . 2 y l p p u s r e w o p 7 k l c sn ii f o t u p n i k c o l c 2 t u p n i t n a r e l o t v 5 , t u p n i c 8t n i _ k l cn it u p n i k c o l c e c n e r e f e r " e u r t " 9c n i _ k l cn it u p n i k c o l c e c n e r e f e r " y r a t n e m e l p m o c " 0 1a d d vr w pv 5 . 2 , y l p p u s r e w o p g o l a n a 8 1c t u o _ b ft u o t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " y r a t n e m e l p m o c " d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a s e h c t i w s . c n i _ b f o t 9 1t t u o _ b ft u o s e h c t i w s t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " " e u r t " o t d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a . t n i _ b f 0 2t n i _ b fn i r o f l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f s e d i v o r p , t u p n i k c a b d e e f " e u r t " . r o r r e e s a h p e t a n i m i l e o t t n i _ k l c h t i w n o i t a z i n o r h c n y s 1 2c n i _ b fn i l l p l a n r e t n i e h t o t l a n g i s s e d i v o r p , t u p n i k c a b d e e f " y r a t n e m e l p m o c " . r o r r e e s a h p e t a n i m i l e o t c n i _ k l c h t i w n o i t a z i n o r h c n y s r o f 2 2 a t a d sn ii r o f t u p n i a t a d 2 t u p n i t n a r e l o t v 5 , t u p n i l a i r e s c
3 ICS93716 0420h?09/10/08 byte 0: output control (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x d e v r e s e r 6 t i b6 1 , 7 11 3 c k l c , 3 t k l c 5 t i b-x d e v r e s e r 4 t i b-x d e v r e s e r 3 t i b-x d e v r e s e r 2 t i b-x d e v r e s e r 1 t i b-x d e v r e s e r 0 t i b-x d e v r e s e r byte 1: output control (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x d e v r e s e r 6 t i b-x d e v r e s e r 5 t i b-x d e v r e s e r 4 t i b-x d e v r e s e r 3 t i b-x d e v r e s e r 2 t i b-x d e v r e s e r 1 t i b-x d e v r e s e r 0 t i b-x d e v r e s e r byte 3: reserved (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x d e v r e s e r 6 t i b-x d e v r e s e r 5 t i b-x d e v r e s e r 4 t i b-x d e v r e s e r 3 t i b-x d e v r e s e r 2 t i b-x d e v r e s e r 1 t i b-x d e v r e s e r 0 t i b-x d e v r e s e r byte 4: reserved (1= enable, 0 = disable) byte 2: reserved (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x d e v r e s e r 6 t i b-x d e v r e s e r 5 t i b-x d e v r e s e r 4 t i b-x d e v r e s e r 3 t i b-x d e v r e s e r 2 t i b-x d e v r e s e r 1 t i b-x d e v r e s e r 0 t i b-x d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) e t o n ( d e v r e s e r 6 t i b-0 ) e t o n ( d e v r e s e r 5 t i b-0 ) e t o n ( d e v r e s e r 4 t i b-0 ) e t o n ( d e v r e s e r 3 t i b-0 ) e t o n ( d e v r e s e r 2 t i b-1 ) e t o n ( d e v r e s e r 1 t i b-1 ) e t o n ( d e v r e s e r 0 t i b-0 ) e t o n ( d e v r e s e r byte 5: reserved (1= enable, 0 = disable) note: don?t write into this register, writing into this register can cause malfunction t i b# n i pd w pn o i t p i r c s e d 7 t i b1 , 21 0 c k l c , 0 t k l c 6 t i b5 , 41 1 c k l c , 1 t k l c 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b4 1 , 3 11 2 c k l c , 2 t k l c 2 t i b7 2 , 6 21 5 c k l c , 5 t k l c 1 t i b-1 d e v r e s e r 0 t i b5 2 , 4 21 4 c k l c , 4 t k l c
4 ICS93716 0420h?09/10/08 absolute maximum ratings supply voltage (vdd & avdd). . . . . . . . . . . -0.5v to 4.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.5v to v dd + 0.5v ambient operating temperature . . . . . . . . . . 0c to +85c storage temperature . . . . . . . . . . . . . . . . . . . -65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 85c; supply voltage avdd, vdd = 2.5 v +/- 0.2v, r l = 120 ? , c l =15pf (unless otherwise stated) parameter symbol conditions min typ max units input high current i ih v i = v dd or gnd 5 a input low current i il v i = v dd or gnd 5 a i dd2.5 r l = 120 ? , c l = 0pf @ 170mhz 250 350 ma i ddpd c l = 0pf 65 90 ma input clamp voltage v ik v ddq = 2.3v iin = -18ma -1.2 v i oh = -1 ma v dd - 0.1 v i oh = -12 ma 1.7 v i ol =1 ma 0.1 v i ol =12 ma 0.6 v input capacitance 1 c in v i = gnd or v dd 3pf output capacitance 1 c out v out = gnd or v dd 3pf 1 guaranteed b y desi g n at 233mhz, not 100% tested in production. operating supply current high-level output voltage v oh low-level output voltage v ol
5 ICS93716 0420h?09/10/08 dc electrical characteristics ( see note1 ) t a = 0 - 85c; supply voltage avdd, vdd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v ddq , a vdd 2.3 2.5 2.7 v clk_int, clk_inc, fb_inc, fb_int 0.4 v dd /2 - 0.18 v sclk, sdata -0.3 0.7 v clk_int, clk_inc, fb_inc, fb_int v dd /2 + 0.18 2.1 v sclk, sdata 1.7 5 v dc input signal voltage (note 2) v in -0.3 v dd + 0.3 v dc - clk_int, clk_inc, fb_inc, fb_int 0.36 v dd + 0.6 v ac - clk_int, clk_inc, fb_inc, fb_int 0.7 v dd + 0.6 v output differential cross- voltage (note 4) v ox v dd /2 - 0.15 v dd /2 + 0.15 v input differential cross- voltage (note 4) v ix v dd /2 - 0.2 v dd /2 v dd /2 + 0.2 v high impedance output current i oz v dd =2.7v, v out =v dd or gnd 0.1 5 a operating free-air temperature t a 085c differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc excursion of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vtr is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v dd and is the voltage at which the differential signal crosses.
6 ICS93716 0420h?09/10/08 notes: 1. refers to transition on noninverting output in pll bypass mode. 2. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle=t wh /t c , were the cycle (t c ) decreases as the frequency goes up. 3. switching characteristics guaranteed for application frequency range. 4. static phase offset shifted by design. timing requirements t a = 0 - 85c; supply voltage avdd, vdd = 2.5 v +/- 0.2v, r l = 120 ? , c l =15pf (unless otherwise parameter symbol conditions min max units max clock frequency 3 freq op 33 233 mhz application frequency range 3 freq app 60 170 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 100 s switching characteristics t a = 0 - 85c; supply voltage avdd, vdd = 2.5 v +/- 0.2v, r l = 120 , c l =15pf (unless otherwise stated) parameter symbol condition min typ max units low-to high level propa g ation dela y time t plh 1 clk_in to any output 5.5 ns high-to low level propagation dela y time t phl 1 clk_in to any output 5.5 ns dut y c y cle dc 49 51 % input clock slew rate t sl ( i ) 14v/ns c y cle to c y cle jitter 1 t c y c -t c y c 100mhz < f < 170mhz 50 65 ps c y cle to c y cle jitter 1 t c y c -t c y c f=66mhz 72 75 ps phase error t (p hase error ) 4 -150 0 150 ps output to output skew t skew 75 100 ps rise time, fall time t r , t f see figure 8 550 950 ps
7 ICS93716 0420h?09/10/08 gnd ICS93716 v dd v dd /2 v (clkc) v (clkc) scope c=15pf -vdd/2 -vdd/2 -vdd/2 vdd/2 z=60 ? z=60 ? z=50 ? z=50 ? r=10 ? r=10 ? r=50 ? r=60 ? r=60 ? r=50 ? v (tt) v (tt) c=15pf note: v (tt) = gnd t c(n) t c(n+1) t jit(cc) =t c(n) t c(n+1) figure 1. ibis model output load figure 2. output load test circuit y , fb_outc x y , fb_outt x parameter measurement information ICS93716 fi g ure 3. c y cle-to-c y cle jitter
8 ICS93716 0420h?09/10/08 (n is a large number of samples) t ( ) n+1 t ()n t () = 1 n= n t ()n n clk_inc clk_int fb_inc fb_int t (skew) y # x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y x parameter measurement information figure 4. static phase offset figure 5. output skew 1 f o t = t - (jit_per) t c(n) c(n) 1 f o figure 6. period jitter
9 ICS93716 0420h?09/10/08 clock inputs and outputs 80% 20% 80% 20% t slr t slf v id ,v od figure 8. input and output slew rates parameter measurement information t jit(hper_n) t jit(hper_n+1) 1 f o y , fb_outc x y , fb_outt x figure 7. half-period jitter t jit(hper) t jit(hper_n) 1 2xf o =-
10 ICS93716 0420h?09/10/08 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 5 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) a ck byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) a ck dummy command code a ck dummy byte count a ck byte 0 a ck byte 1 a ck byte 2 a ck byte 3 a ck byte 4 a ck byte 5 a ck stop bit how to write:
11 ICS93716 0420h?09/10/08 seating plane seating plane a1 a a2 e -c- - c - b .10 (.004) c .10 (.004) c c l index area index area 12 1 2 n d e1 e ordering information 93716 y flf-t designation for tape and reel packaging annealed lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type example: xxxxx y f lf - t min max min max a -- 2.00 -- .079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n
12 ICS93716 0420h?09/10/08 ordering information 93716 y glf-t example: xxxxx y glf - t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c 6.10 mm. body, 0.65 mm. pitch tssop (240 mil) (25.6 mil) min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .012 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 28 9.60 9.80 .378 .386 10-0039 symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.65 basic 0.0256 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153 designation for tape and reel packaging annealed lead free (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type
13 ICS93716 0420h?09/10/08 revision history rev. issue date description page # h 9/10/2008 updated product description/features 1

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